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RISC-V Summit 2023 has ended
November 7-8, 2023
Santa Clara, CA
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Wednesday, November 8 • 1:55pm - 2:15pm
Adoption of ISO 26262 for RISC-V - Ravindranath Munnan, Imagination Technologies

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Authors: Poorva Bhargava & Ravindranath Munnan, Imagination Technologies

The RISC-V ISA is evolving to create an infrastructure which is modular and supports custom instructions. This unique feature of RISC-V is enabling a wide range of specialized processors and accelerators to be developed. Furthermore, RISC-V microprocessors are of vested interest in safety applications for the same reasons, owing to its open ISA model and inherent flexibility. Nonetheless, automotive grade RISC-V Hardware and Software must adhere to the guidelines of ISO26262 where safety functionality is concerned. For what is historically an open and flexible, agile, ISA, this poses a potential challenge when adopting and adhering to the expectations outlined in ISO26262 throughout the entire lifecycle. The aim of this paper therefore is to consider the Features, Strengths, and Limitations of RISC- V ISA and Functional Safety / ISO26262 standards, the challenges and threats posed by ISO26262 guidelines in the domain of Open-standard ISA, the challenges in adoption of ISO26262 for RISC-V, Key considerations for using RISC-V based Hardware in safety-critical applications complying to ISO26262; Open-source ISA Evolution and maintaining ISO26262 compliance.

Speakers
avatar for Ravindranath Munnan

Ravindranath Munnan

Senior Principal Engineer, Imagination Technologies
Ravi is a Technical Lead for CPU Hardware Design at Imagination Technologies. His primary area of interest is on Real time CPU Microarchitecture, Functional Safety, Design and Methodologies. With over 23 years of experience in Top 10 semiconductors industries like ST Microelectronics... Read More →


Wednesday November 8, 2023 1:55pm - 2:15pm PST
Theater (Level 2)
  Software/Automotive/Embedded